﻿

    public sealed class GPggIO
    {
        #region Private's...

        private UInt32 _MODER = 0x00;
        private UInt32 _OTYPER = 0x04;
        private UInt32 _OSPEEDR = 0x08;
        private UInt32 _PUPDR = 0x0C;
        private UInt32 _IDR = 0x10;
        private UInt32 _ODR = 0x14;
        private UInt32 _BSRRL = 0x18;
        private UInt32 _BSRRH = 0x1A;
        private UInt32 _LCKR = 0x1C;

        // Alternate Function Number 
        private UInt32[] AFR = new UInt32[] { 0x12, 0x12, 0x22, 0x22, 0x22, 0, 0, 0x32, 0x32, 0x32, 0x32, 0x92, 0x92, 0x92 }; // AF1/2/3/9}

        #endregion

        #region Properties...

        /// <summary>
        /// GPIO port mode register, Address offset: 0x00
        /// </summary>
        public UInt32 MODER { get { return _MODER; } set { _MODER = value; } }

        /// <summary>
        /// GPIO port output type register, Address offset: 0x04
        /// </summary>
        public UInt32 OTYPER { get { return _OTYPER; } set { _OTYPER = value; } }

        /// <summary>
        /// GPIO port output speed register, Address offset: 0x08
        /// </summary>
        public UInt32 OSPEEDR { get { return _OSPEEDR; } set { _OSPEEDR = value; } }

        /// <summary>
        /// GPIO port pull-up/pull-down register, Address offset: 0x0C
        /// </summary>
        public UInt32 PUPDR { get { return _PUPDR; } set { _PUPDR = value; } }

        /// <summary>
        /// GPIO port input data register, Address offset: 0x10 
        /// </summary>
        public UInt32 IDR { get { return _IDR; } set { _IDR = value; } }

        /// <summary>
        /// GPIO port output data register, Address offset: 0x14
        /// </summary>
        public UInt32 ODR { get { return _ODR; } set { _ODR = value; } }

        /// <summary>
        /// GPIO port bit set/reset low register, Address offset: 0x18
        /// </summary>
        public UInt32 BSRRL { get { return _BSRRL; } set { _BSRRL = value; } }

        /// <summary>
        /// GPIO port bit set/reset high register, Address offset: 0x1A
        /// </summary>
        public UInt32 BSRRH { get { return _BSRRH; } set { _BSRRH = value; } }

        /// <summary>
        /// GPIO port configuration lock register, Address offset: 0x1C
        /// </summary>
        public UInt32 LCKR { get { return _LCKR; } set { _LCKR = value; } }

        /// <summary>
        /// GPIO alternate function registers, Address offset: 0x20-0x24
        /// </summary>
        // public UInt32 AFR { get { return _AFR; } set { _AFR = value; } }    

        #endregion

        #region Registers...

        /// <summary>
        /// GPIO port mode register, Address offset: 0x00
        /// </summary>
        public Register MODER_Register;

        /// <summary>
        /// GPIO port output type register, Address offset: 0x04
        /// </summary>
        public Register OTYPER_Register;

        /// <summary>
        /// GPIO port output speed register, Address offset: 0x08
        /// </summary>
        public Register OSPEEDR_Register;

        /// <summary>
        /// GPIO port pull-up/pull-down register, Address offset: 0x0C
        /// </summary>
        public Register PUPDR_Register;

        /// <summary>
        /// GPIO port input data register, Address offset: 0x10 
        /// </summary>
        public Register IDR_Register;

        /// <summary>
        /// GPIO port output data register, Address offset: 0x14
        /// </summary>
        public Register ODR_Register;

        /// <summary>
        /// GPIO port bit set/reset low register, Address offset: 0x18
        /// </summary>
        public Register BSRRL_Register;

        /// <summary>
        /// GPIO port bit set/reset high register, Address offset: 0x1A
        /// </summary>
        public Register BSRRH_Register;

        /// <summary>
        /// GPIO port configuration lock register, Address offset: 0x1C
        /// </summary>
        public Register LCKR_Register;

        /// <summary>
        /// GPIO alternate function registers, Address offset: 0x20-0x24
        /// </summary>
        // public Register AFR[2];    

        #endregion

        /// <summary>
        /// GPIOA. Class Type for defining the GPIOA Register Types...
        /// </summary>
        public static GPIO GPIOA = new GPIO(STM32F4xx.GPIOA_BASE);

        /// <summary>
        /// GPIOB. Class Type for defining the GPIOB Register Types...
        /// </summary>
        public static GPIO GPIOB = new GPIO(STM32F4xx.GPIOB_BASE);

        public GPIO(UInt32 GPIOx_BASE)
        {
            MODER_Register = new Register(GPIOx_BASE + MODER);
            OTYPER_Register = new Register(GPIOx_BASE + OTYPER);
            OSPEEDR_Register = new Register(GPIOx_BASE + OSPEEDR);
            PUPDR_Register = new Register(GPIOx_BASE + PUPDR);
            IDR_Register = new Register(GPIOx_BASE + IDR);
            ODR_Register = new Register(GPIOx_BASE + ODR);
            BSRRL_Register = new Register(GPIOx_BASE + BSRRL);
            BSRRH_Register = new Register(GPIOx_BASE + BSRRH);
            LCKR_Register = new Register(GPIOx_BASE + LCKR);
        }
    } // END of Class...

    /// <summary>
    /// See: P.147 - Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
    /// </summary>
    public sealed class ResetCounterControl
    {
        #region Private's...

        private uint _CR = 0x00;
        private uint _PLLCFGR = 0x04;
        private uint _CFGR = 0x08;
        private uint _CIR = 0x0C;
        private uint _AHB1RSTR = 0x10;
        private uint _AHB2RSTR = 0x14;
        private uint _AHB3RSTR = 0x18;
        //private uint _RESERVED0 = 0x1C;
        private uint _APB1RSTR = 0x20;
        private uint _APB2RSTR = 0x24;
        //private uint _RESERVED1 = 0x28 - 0x2C;
        private uint _AHB1ENR = 0x30;
        private uint _AHB2ENR = 0x34;
        private uint _AHB3ENR = 0x38;
        //private uint _RESERVED2 = 0x3C;
        private uint _APB1ENR = 0x40;
        private uint _APB2ENR = 0x44;
        //private uint _RESERVED3 = 0x48 - 0x4C;
        private uint _AHB1LPENR = 0x50;
        private uint _AHB2LPENR = 0x54;
        private uint _AHB3LPENR = 0x58;
        private uint _RESERVED4 = 0x5C;
        private uint _APB1LPENR = 0x60;
        private uint _APB2LPENR = 0x64;
        //private uint _RESERVED5 = 0x68 - 0x6C;
        private uint _BDCR = 0x70;
        private uint _CSR = 0x74;
        //private uint _RESERVED6 = 0x78 - 0x7C;
        private uint _SSCGR = 0x80;
        private uint _PLLI2SCFGR = 0x84;

        #endregion

        #region Properties...

        /// <summary>
        /// RCC clock control register, Address offset: 0x00
        /// </summary>
        public uint CR { get { return _CR; } set { _CR = value; } }

        /// <summary>
        /// RCC PLL configuration register, Address offset: 0x04
        /// </summary>
        public uint PLLCFGR { get { return _PLLCFGR; } set { _PLLCFGR = value; } }

        /// <summary>
        /// RCC clock configuration register, Address offset: 0x08
        /// </summary>
        public uint CFGR { get { return _CFGR; } set { _CFGR = value; } }

        /// <summary>
        /// RCC clock interrupt register, Address offset: 0x0C
        /// </summary>
        public uint CIR { get { return _CIR; } set { _CIR = value; } }

        /// <summary>
        /// RCC AHB1 peripheral reset register, Address offset: 0x10
        /// </summary>
        public uint AHB1RSTR { get { return _AHB1RSTR; } set { _AHB1RSTR = value; } }

        /// <summary>
        /// RCC AHB2 peripheral reset register, Address offset: 0x14
        /// </summary>
        public uint AHB2RSTR { get { return _AHB2RSTR; } set { _AHB2RSTR = value; } }

        /// <summary>
        /// RCC AHB3 peripheral reset register, Address offset: 0x18
        /// </summary>
        public uint AHB3RSTR { get { return _AHB3RSTR; } set { _AHB3RSTR = value; } }

        /// <summary>
        /// Reserved, 0x1C
        /// </summary>
        // public uint RESERVED0 { get { return _RESERVED0; } set { _RESERVED0 = value; } }       

        /// <summary>
        /// RCC APB1 peripheral reset register, Address offset: 0x20
        /// </summary>
        public uint APB1RSTR { get { return _APB1RSTR; } set { _APB1RSTR = value; } }

        /// <summary>
        /// RCC APB2 peripheral reset register, Address offset: 0x24
        /// </summary>
        public uint APB2RSTR { get { return _APB2RSTR; } set { _APB2RSTR = value; } }

        //public uint RESERVED1 { get { return _RESERVED1; } set { _RESERVED1 = value; } }  Reserved, 0x28-0x2C

        /// <summary>
        /// RCC AHB1 peripheral clock register, Address offset: 0x30
        /// </summary>
        public uint AHB1ENR { get { return _AHB1ENR; } set { _AHB1ENR = value; } }

        /// <summary>
        /// RCC AHB2 peripheral clock register, Address offset: 0x34
        /// </summary>
        public uint AHB2ENR { get { return _AHB2ENR; } set { _AHB2ENR = value; } }

        /// <summary>
        /// RCC AHB3 peripheral clock register, Address offset: 0x38
        /// </summary>
        public uint AHB3ENR { get { return _AHB3ENR; } set { _AHB3ENR = value; } }

        /// <summary>
        ///  Reserved, 0x3C
        /// </summary>
        // public uint RESERVED2 { get { return _RESERVED2; } set { _RESERVED2 = value; } }          

        /// <summary>
        /// RCC APB1 peripheral clock enable register, Address offset: 0x40
        /// </summary>
        public uint APB1ENR { get { return _APB1ENR; } set { _APB1ENR = value; } }

        /// <summary>
        /// RCC APB2 peripheral clock enable register, Address offset: 0x44
        /// </summary>
        public uint APB2ENR { get { return _APB2ENR; } set { _APB2ENR = value; } }

        /// <summary>
        /// Reserved, 0x48-0x4C
        /// </summary>
        //public uint RESERVED3 { get { return _RESERVED3; } set { _RESERVED3 = value; } }   

        /// <summary>
        /// RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50
        /// </summary>
        public uint AHB1LPENR { get { return _AHB1LPENR; } set { _AHB1LPENR = value; } }

        /// <summary>
        /// RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54
        /// </summary>
        public uint AHB2LPENR { get { return _AHB2LPENR; } set { _AHB2LPENR = value; } }

        /// <summary>
        /// RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58
        /// </summary>
        public uint AHB3LPENR { get { return _AHB3LPENR; } set { _AHB3LPENR = value; } }

        /// <summary>
        /// Reserved, 0x5C
        /// </summary>
        // public uint RESERVED4 { get { return _RESERVED4; } set { _RESERVED4 = value; } }             

        /// <summary>
        /// RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60
        /// </summary>
        public uint APB1LPENR { get { return _APB1LPENR; } set { _APB1LPENR = value; } }

        /// <summary>
        /// RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64
        /// </summary>
        public uint APB2LPENR { get { return _APB2LPENR; } set { _APB2LPENR = value; } }

        /// <summary>
        /// Reserved, 0x68-0x6C
        /// </summary>
        //public uint RESERVED5 { get { return _RESERVED5; } set { _RESERVED5 = value; } }           

        /// <summary>
        /// RCC Backup domain control register, Address offset: 0x70 
        /// </summary>
        public uint BDCR { get { return _BDCR; } set { _BDCR = value; } }

        /// <summary>
        /// RCC clock control & status register, Address offset: 0x74
        /// </summary>
        public uint CSR { get { return _CSR; } set { _CSR = value; } }

        /// <summary>
        /// Reserved, 0x78-0x7C 
        /// </summary>
        // public uint RESERVED6 { get { return _RESERVED6; } set { _RESERVED6 = value; } }            

        /// <summary>
        /// RCC spread spectrum clock generation register, Address offset: 0x80
        /// </summary>
        public uint SSCGR { get { return _SSCGR; } set { _SSCGR = value; } }

        /// <summary>
        /// RCC PLLI2S configuration register, Address offset: 0x84
        /// </summary>
        public uint PLLI2SCFGR { get { return _PLLI2SCFGR; } set { _PLLI2SCFGR = value; } }

        #endregion

        #region Registers...

        /// <summary>
        /// RCC clock control register, Address offset: 0x00
        /// </summary>
        public Register CR_Register;

        /// <summary>
        /// RCC PLL configuration register, Address offset: 0x04
        /// </summary>
        public Register PLLCFGR_Register;

        /// <summary>
        /// RCC clock configuration register, Address offset: 0x08
        /// </summary>
        public Register CFGR_Register;

        /// <summary>
        /// RCC clock interrupt register, Address offset: 0x0C
        /// </summary>
        public Register CIR_Register;

        /// <summary>
        /// RCC AHB1 peripheral reset register, Address offset: 0x10
        /// </summary>
        public Register AHB1RSTR_Register;

        /// <summary>
        /// RCC AHB2 peripheral reset register, Address offset: 0x14
        /// </summary>
        public Register AHB2RSTR_Register;

        /// <summary>
        /// RCC AHB3 peripheral reset register, Address offset: 0x18
        /// </summary>
        public Register AHB3RSTR_Register;

        /// <summary>
        /// RCC APB1 peripheral reset register, Address offset: 0x20
        /// </summary>
        public Register APB1RSTR_Register;

        /// <summary>
        /// RCC APB2 peripheral reset register, Address offset: 0x24
        /// </summary>
        public Register APB2RSTR_Register;

        /// <summary>
        /// RCC AHB1 peripheral clock register, Address offset: 0x30
        /// </summary>
        public Register AHB1ENR_Register;

        /// <summary>
        /// RCC AHB2 peripheral clock register, Address offset: 0x34
        /// </summary>
        public Register AHB2ENR_Register;

        /// <summary>
        /// RCC AHB3 peripheral clock register, Address offset: 0x38
        /// </summary>
        public Register AHB3ENR_Register;

        /// <summary>
        /// RCC APB1 peripheral clock enable register, Address offset: 0x40
        /// </summary>
        public Register APB1ENR_Register;

        /// <summary>
        /// RCC APB2 peripheral clock enable register, Address offset: 0x44
        /// </summary>
        public Register APB2ENR_Register;

        /// <summary>
        /// RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50
        /// </summary>
        public Register AHB1LPENR_Register;

        /// <summary>
        /// RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54
        /// </summary>
        public Register AHB2LPENR_Register;

        /// <summary>
        /// RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58
        /// </summary>
        public Register AHB3LPENR_Register;

        /// <summary>
        /// RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60
        /// </summary>
        public Register APB1LPENR_Register;

        /// <summary>
        /// RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64
        /// </summary>
        public Register APB2LPENR_Register;

        /// <summary>
        /// RCC Backup domain control register, Address offset: 0x70
        /// </summary>
        public Register BDCR_Register;

        /// <summary>
        /// RCC clock control and status register, Address offset: 0x74
        /// </summary>
        public Register CSR_Register;

        /// <summary>
        /// RCC spread spectrum clock generation register, Address offset: 0x80
        /// </summary>
        public Register SSCGR_Register;

        /// <summary>
        /// RCC PLLI2S configuration register, Address offset: 0x84
        /// </summary>
        public Register PLLI2SCFGR_Register;

        #endregion

        /// <summary>
        /// Reset and Counter Control. Class Type for defining the Reset and Counter Control Registers...
        /// P.159 for RCC registers...
        /// </summary>
        public static ResetCounterControl RCC = new ResetCounterControl();

        public ResetCounterControl()
        {
            CR_Register = new Register(STM32F4xx.RCC_BASE + CR);
            PLLCFGR_Register = new Register(STM32F4xx.RCC_BASE + PLLCFGR);
            CFGR_Register = new Register(STM32F4xx.RCC_BASE + CFGR);
            CIR_Register = new Register(STM32F4xx.RCC_BASE + CIR);
            AHB1RSTR_Register = new Register(STM32F4xx.RCC_BASE + AHB1RSTR);
            AHB2RSTR_Register = new Register(STM32F4xx.RCC_BASE + AHB2RSTR);
            AHB3RSTR_Register = new Register(STM32F4xx.RCC_BASE + AHB3RSTR);
            APB1RSTR_Register = new Register(STM32F4xx.RCC_BASE + APB1RSTR);
            APB2RSTR_Register = new Register(STM32F4xx.RCC_BASE + APB2RSTR);
            AHB1ENR_Register = new Register(STM32F4xx.RCC_BASE + AHB1ENR);
            AHB2ENR_Register = new Register(STM32F4xx.RCC_BASE + AHB2ENR);
            AHB3ENR_Register = new Register(STM32F4xx.RCC_BASE + AHB3ENR);
            APB1ENR_Register = new Register(STM32F4xx.RCC_BASE + APB1ENR);
            APB2ENR_Register = new Register(STM32F4xx.RCC_BASE + APB2ENR);
            AHB1LPENR_Register = new Register(STM32F4xx.RCC_BASE + AHB1LPENR);
            AHB2LPENR_Register = new Register(STM32F4xx.RCC_BASE + AHB2LPENR);
            AHB3LPENR_Register = new Register(STM32F4xx.RCC_BASE + AHB3LPENR);
            APB1LPENR_Register = new Register(STM32F4xx.RCC_BASE + APB1LPENR);
            APB2LPENR_Register = new Register(STM32F4xx.RCC_BASE + APB2LPENR);
            BDCR_Register = new Register(STM32F4xx.RCC_BASE + BDCR);
            CSR_Register = new Register(STM32F4xx.RCC_BASE + CSR);
            SSCGR_Register = new Register(STM32F4xx.RCC_BASE + SSCGR);
            PLLI2SCFGR_Register = new Register(STM32F4xx.RCC_BASE + PLLI2SCFGR);
        }

    } // END of Class...

    public sealed class CPUggimer
    {
        // 17.3.20 Timer synchronization
        // The TIM timers are linked together internally for timer synchronization or chaining. Refer to
        // Section 18.3.15: Timer synchronization on page 605 for details.

        #region Private's...

        private uint _CR1 = 0x00;
        private uint _RESERVED0 = 0x02;
        private uint _CR2 = 0x04;
        private uint _RESERVED1 = 0x06;
        private uint _SMCR = 0x08;
        private uint _RESERVED2 = 0x0A;
        private uint _DIER = 0x0C;
        private uint _RESERVED3 = 0x0E;
        private uint _SR = 0x10;
        private uint _RESERVED4 = 0x12;
        private uint _EGR = 0x14;
        private uint _RESERVED5 = 0x16;
        private uint _CCMR1 = 0x18;
        private uint _RESERVED6 = 0x1A;
        private uint _CCMR2 = 0x1C;
        private uint _RESERVED7 = 0x1E;
        private uint _CCER = 0x20;
        private uint _RESERVED8 = 0x22;
        private uint _CNT = 0x24;
        private uint _PSC = 0x28;
        private uint _RESERVED9 = 0x2A;
        private uint _ARR = 0x2C;
        private uint _RCR = 0x30;
        private uint _RESERVED10 = 0x32;
        private uint _CCR1 = 0x34;
        private uint _CCR2 = 0x38;
        private uint _CCR3 = 0x3C;
        private uint _CCR4 = 0x40;
        private uint _BDTR = 0x44;
        private uint _RESERVED11 = 0x46;
        private uint _DCR = 0x48;
        private uint _RESERVED12 = 0x4A;
        private uint _DMAR = 0x4C;
        private uint _RESERVED13 = 0x4E;
        private uint _OR = 0x50;
        private uint _RESERVED14 = 0x52;

        #endregion

        #region Properties...

        /// <summary>
        /// TIM control register 1, Address offset: 0x00
        /// </summary>
        public uint CR1 { get { return _CR1; } set { _CR1 = value; } }

        /// <summary>
        /// Reserved, 0x02
        /// </summary>
        public uint RESERVED0 { get { return _RESERVED0; } }

        /// <summary>
        /// TIM control register 2, Address offset: 0x04 
        /// </summary>
        public uint CR2 { get { return _CR2; } set { _CR2 = value; } }

        /// <summary>
        /// Reserved, 0x06 
        /// </summary>
        public uint RESERVED1 { get { return _RESERVED1; } }

        /// <summary>
        /// TIM slave mode control register, Address offset: 0x08 
        /// </summary>
        public uint SMCR { get { return _SMCR; } set { _SMCR = value; } }

        /// <summary>
        /// Reserved, 0x0A 
        /// </summary>
        public uint RESERVED2 { get { return _RESERVED2; } }

        /// <summary>
        /// TIM DMA/interrupt enable register, Address offset: 0x0C
        /// </summary>
        public uint DIER { get { return _DIER; } set { _DIER = value; } }

        /// <summary>
        /// Reserved, 0x0E
        /// </summary>
        public uint RESERVED3 { get { return _RESERVED3; } }

        /// <summary>
        /// TIM status register, Address offset: 0x10
        /// </summary>
        public uint SR { get { return _SR; } set { _SR = value; } }

        /// <summary>
        /// Reserved, 0x12 
        /// </summary>
        public uint RESERVED4 { get { return _RESERVED4; } }

        /// <summary>
        /// TIM event generation register, Address offset: 0x14 
        /// </summary>
        public uint EGR { get { return _EGR; } set { _EGR = value; } }

        /// <summary>
        /// Reserved, 0x16
        /// </summary>
        public uint RESERVED5 { get { return _RESERVED5; } }

        /// <summary>
        /// TIM capture/compare mode register 1, Address offset: 0x18 
        /// </summary>
        public uint CCMR1 { get { return _CCMR1; } set { _CCMR1 = value; } }

        /// <summary>
        /// Reserved, 0x1A
        /// </summary>
        public uint RESERVED6 { get { return _RESERVED6; } }

        /// <summary>
        /// TIM capture/compare mode register 2, Address offset: 0x1C 
        /// </summary>
        public uint CCMR2 { get { return _CCMR2; } set { _CCMR2 = value; } }

        /// <summary>
        /// Reserved, 0x1E
        /// </summary>
        public uint RESERVED7 { get { return _RESERVED7; } }

        /// <summary>
        /// TIM capture/compare enable register, Address offset: 0x20 
        /// </summary>
        public uint CCER { get { return _CCER; } set { _CCER = value; } }

        /// <summary>
        /// Reserved, 0x22 
        /// </summary>
        public uint RESERVED8 { get { return _RESERVED8; } }

        /// <summary>
        /// TIM counter register, Address offset: 0x24 
        /// </summary>
        public uint CNT { get { return _CNT; } set { _CNT = value; } }

        /// <summary>
        /// TIM prescaler, Address offset: 0x28 
        /// </summary>
        public uint PSC { get { return _PSC; } set { _PSC = value; } }

        /// <summary>
        /// Reserved, 0x2A 
        /// </summary>
        public uint RESERVED9 { get { return _RESERVED9; } }

        /// <summary>
        /// TIM auto-reload register, Address offset: 0x2C 
        /// </summary>
        public uint ARR { get { return _ARR; } set { _ARR = value; } }

        /// <summary>
        /// TIM repetition counter register, Address offset: 0x30
        /// </summary>
        public uint RCR { get { return _RCR; } set { _RCR = value; } }

        /// <summary>
        /// Reserved, 0x32
        /// </summary>
        public uint RESERVED10 { get { return _RESERVED10; } }

        /// <summary>
        /// TIM capture/compare register 1, Address offset: 0x34 
        /// </summary>
        public uint CCR1 { get { return _CCR1; } set { _CCR1 = value; } }

        /// <summary>
        /// TIM capture/compare register 2, Address offset: 0x38
        /// </summary>
        public uint CCR2 { get { return _CCR2; } set { _CCR2 = value; } }

        /// <summary>
        /// TIM capture/compare register 3, Address offset: 0x3C
        /// </summary>
        public uint CCR3 { get { return _CCR3; } set { _CCR3 = value; } }

        /// <summary>
        /// TIM capture/compare register 4, Address offset: 0x40 
        /// </summary>
        public uint CCR4 { get { return _CCR4; } set { _CCR4 = value; } }

        /// <summary>
        /// TIM break and dead-time register, Address offset: 0x44
        /// </summary>
        public uint BDTR { get { return _BDTR; } set { _BDTR = value; } }

        /// <summary>
        /// Reserved, 0x46 
        /// </summary>
        public uint RESERVED11 { get { return _RESERVED11; } }

        /// <summary>
        /// TIM DMA control register, Address offset: 0x48
        /// </summary>
        public uint DCR { get { return _DCR; } set { _DCR = value; } }

        /// <summary>
        /// Reserved, 0x4A
        /// </summary>
        public uint RESERVED12 { get { return _RESERVED12; } }

        /// <summary>
        /// TIM DMA address for full transfer, Address offset: 0x4C
        /// </summary>
        public uint DMAR { get { return _DMAR; } set { _DMAR = value; } }

        /// <summary>
        /// Reserved, 0x4E 
        /// </summary>
        public uint RESERVED13 { get { return _RESERVED13; } }

        /// <summary>
        /// TIM option register, Address offset: 0x50
        /// </summary>
        public uint OR { get { return _OR; } set { _OR = value; } }

        /// <summary>
        /// Reserved, 0x52
        /// </summary>
        public uint RESERVED14 { get { return _RESERVED14; } }

        #endregion

        #region Timer Registers...

        ////////////////////////////////////////////////////////////////////////////////
        // See P.574 on the TIM1 and TIM8 Register table...                           //
        ////////////////////////////////////////////////////////////////////////////////
        /// <summary>
        /// control register 1 (TIMx_CR1) - Address offset: 0x00 - Reset value: 0x0000
        /// </summary>
        public Register CR1_Register;

        /// <summary>
        /// control register 2 (TIMx_CR2) - Address offset: 0x04 - Reset value: 0x0000
        /// </summary>
        public Register CR2_Register;

        /// <summary>
        /// slave mode control register (TIMx_SMCR) - Address offset: 0x08 - Reset value: 0x0000
        /// </summary>
        public Register SMCR_Register;

        /// <summary>
        /// DMA/interrupt enable register (TIMx_DIER) - Address offset: 0x0C - Reset value: 0x0000
        /// </summary>
        public Register DIER_Register;

        /// <summary>
        /// status register (TIMx_SR) - Address offset: 0x10 - Reset value: 0x0000
        /// </summary>
        public Register SR_Register;

        /// <summary>
        /// event generation register (TIMx_EGR) - Address offset: 0x14 - Reset value: 0x0000
        /// </summary>
        public Register EGR_Register;

        /// <summary>
        /// capture/compare mode register 1 (TIMx_CCMR1) - Address offset: 0x18 - Reset value: 0x0000
        /// </summary>
        public Register CCMR1_Register;

        /// <summary>
        /// capture/compare mode register 2 (TIMx_CCMR2) - Address offset: 0x1C - Reset value: 0x0000
        /// </summary>
        public Register CCMR2_Register;

        /// <summary>
        /// capture/compare enable register (TIMx_CCER) - Address offset: 0x20 - Reset value: 0x0000
        /// </summary>
        public Register CCER_Register;

        /// <summary>
        /// counter (TIMx_CNT) - Address offset: 0x24 - Reset value: 0x0000
        /// </summary>
        public Register CNT_Register;

        /// <summary>
        /// prescaler (TIMx_PSC) - Address offset: 0x28 - Reset value: 0x0000
        /// </summary>
        public Register PSC_Register;

        /// <summary>
        /// auto-reload register (TIMx_ARR) - Address offset: 0x2C - Reset value: 0x0000
        /// </summary>
        public Register ARR_Register;

        /// <summary>
        /// repetition counter register (TIMx_RCR) - Address offset: 0x30 - Reset value: 0x0000
        /// </summary>
        public Register RCR_Register;

        /// <summary>
        /// Capture/compare register 1 (TIMx_CCR1) - Address offset: 0x34 - Reset value: 0x0000
        /// </summary>
        public Register CCR1_Register;

        /// <summary>
        /// Capture/compare register 2 (TIMx_CCR2) - Address offset: 0x38 - Reset value: 0x0000
        /// </summary>
        public Register CCR2_Register;

        /// <summary>
        /// Capture/compare register 3 (TIMx_CCR3) - Address offset: 0x3C - Reset value: 0x0000
        /// </summary>
        public Register CCR3_Register;

        /// <summary>
        /// Capture/compare register 4 (TIMx_CCR4) - Address offset: 0x40 - Reset value: 0x0000
        /// </summary>
        public Register CCR4_Register;

        /// <summary>
        /// Break and dead-time register (TIMx_BDTR) - Address offset: 0x44 - Reset value: 0x0000
        /// </summary>
        public Register BDTR_Register;

        /// <summary>
        /// DMA control register (TIMx_DCR) - Address offset: 0x48 - Reset value: 0x0000
        /// </summary>
        public Register DCR_Register;

        /// <summary>
        /// DMA address for full transfer (TIMx_DMAR) - Address offset: 0x4C - Reset value: 0x0000
        /// </summary>
        public Register DMAR_Register;

        #endregion

        ////////////////////////////////////////////////////////////////////////////////////////
        // System Timer Configuration                                                         //
        // STM32F4_32B_TIMER = 5                                                              //
        // STM32F4_16B_TIMER = 12                                                             //
        ////////////////////////////////////////////////////////////////////////////////////////
        // public static CPUTimer TIMER1 = new CPUTimer(STM32F4xx.TIMER1_BASE);
        // public static CPUTimer TIMER2 = new CPUTimer(STM32F4xx.TIMER2_BASE);
        // public static CPUTimer TIMER3 = new CPUTimer(STM32F4xx.TIMER3_BASE);
        // public static CPUTimer TIMER4 = new CPUTimer(STM32F4xx.TIMER4_BASE);
        // public static CPUTimer TIMER5 = new CPUTimer(STM32F4xx.TIMER5_BASE);
        // public static CPUTimer TIMER6 = new CPUTimer(STM32F4xx.TIMER6_BASE);
        // public static CPUTimer TIMER7 = new CPUTimer(STM32F4xx.TIMER7_BASE);

        /// <summary>
        /// Provids Access to the Timer 8 Configuration Registers...
        /// See: P.548 for TIM1&TIM8 registers...
        /// </summary>
        public static CPUTimer TIMER8 = new CPUTimer(STM32F4xx.TIM8_BASE);

        // public static CPUTimer TIMER9 = new CPUTimer(STM32F4xx.TIMER9_BASE);
        // public static CPUTimer TIMER10 = new CPUTimer(STM32F4xx.TIMER10_BASE);
        // public static CPUTimer TIMER11 = new CPUTimer(STM32F4xx.TIMER11_BASE);
        // public static Timer TIMER12 = new Timer(STM32F4xx.TIMER12_BASE);
        // public static CPUTimer TIMER13 = new CPUTimer(STM32F4xx.TIMER13_BASE);
        // public static CPUTimer TIMER14 = new CPUTimer(STM32F4xx.TIMER14_BASE);

        public CPUTimer(UInt32 TIMx_BASE)
        {
            // See: P.611 for TIM2 to TIM5 registers...
            
            CR1_Register = new Register(TIMx_BASE + CR1);
            CR2_Register = new Register(TIMx_BASE + CR2);
            SMCR_Register = new Register(TIMx_BASE + SMCR);
            DIER_Register = new Register(TIMx_BASE + DIER);
            SR_Register = new Register(TIMx_BASE + SR);
            EGR_Register = new Register(TIMx_BASE + EGR);
            CCMR1_Register = new Register(TIMx_BASE + CCMR1);
            CCMR2_Register = new Register(TIMx_BASE + CCMR2);
            CCER_Register = new Register(TIMx_BASE + CCER);
            CNT_Register = new Register(TIMx_BASE + CNT);
            PSC_Register = new Register(TIMx_BASE + PSC);
            ARR_Register = new Register(TIMx_BASE + ARR);
            RCR_Register = new Register(TIMx_BASE + RCR);
            CCR1_Register = new Register(TIMx_BASE + CCR1);
            CCR2_Register = new Register(TIMx_BASE + CCR2);
            CCR3_Register = new Register(TIMx_BASE + CCR3);
            CCR4_Register = new Register(TIMx_BASE + CCR4);
            BDTR_Register = new Register(TIMx_BASE + BDTR);
            DCR_Register = new Register(TIMx_BASE + DCR);
            DMAR_Register = new Register(TIMx_BASE + DMAR);
        }

    } // END of Class...

    public sealed class AnalogToDigitalConverter
    {
        #region Privates...

        private UInt32 _CSR = STM32F4xx.ADC1_BASE + 0x300;
        private UInt32 _CCR = STM32F4xx.ADC1_BASE + 0x304;
        private UInt32 _CDR = STM32F4xx.ADC1_BASE + 0x308;     

        private UInt32 _SR = 0x00;  
        private UInt32 _CR1 = 0x04;   
        private UInt32 _CR2 = 0x08;   
        private UInt32 _SMPR1 = 0x0C; 
        private UInt32 _SMPR2 = 0x10;  
        private UInt32 _JOFR1 = 0x14;  
        private UInt32 _JOFR2 = 0x18;   
        private UInt32 _JOFR3 = 0x1C;   
        private UInt32 _JOFR4 = 0x20;  
        private UInt32 _HTR = 0x24;
        private UInt32 _LTR = 0x28; 
        private UInt32 _SQR1 = 0x2C;
        private UInt32 _SQR2 = 0x30;  
        private UInt32 _SQR3 = 0x34;  
        private UInt32 _JSQR = 0x38;  
        private UInt32 _JDR1 = 0x3C;   
        private UInt32 _JDR2 = 0x40;   
        private UInt32 _JDR3 = 0x44;  
        private UInt32 _JDR4 = 0x48;  
        private UInt32 _DR = 0x4C; 

        #endregion

        #region Properties...

        /// <summary>
        /// ADC Common status register, Address offset: ADC1 base address + 0x300 
        /// </summary>
        public UInt32 CSR { get { return _CSR; } set { _CSR = value; } }

        /// <summary>
        /// ADC common control register, Address offset: ADC1 base address + 0x304
        /// </summary>
        public UInt32 CCR { get { return _CCR; } set { _CCR = value; } }

        /// <summary>
        /// ADC common regular data register for dual AND triple modes, Address offset: ADC1 base address + 0x308
        /// </summary>
        public UInt32 CDR { get { return _CDR; } set { _CDR = value; } }

        /// <summary>
        /// ADC status register, Address offset: 0x00
        /// </summary>
        public UInt32 SR { get { return _SR; } set { _SR = value; } }

        /// <summary>
        /// ADC control register 1, Address offset: 0x04
        /// </summary>
        public UInt32 CR1 { get { return _CR1; } set { _CR1 = value; } }

        /// <summary>
        /// ADC control register 2, Address offset: 0x08
        /// </summary>
        public UInt32 CR2 { get { return _CR2; } set { _CR2 = value; } }

        /// <summary>
        /// ADC sample time register 1, Address offset: 0x0C
        /// </summary>
        public UInt32 SMPR1 { get { return _SMPR1; } set { _SMPR1 = value; } }

        /// <summary>
        /// ADC sample time register 2, Address offset: 0x10 
        /// </summary>
        public UInt32 SMPR2 { get { return _SMPR2; } set { _SMPR2 = value; } }

        /// <summary>
        /// ADC injected channel data offset register 1, Address offset: 0x14
        /// </summary>
        public UInt32 JOFR1 { get { return _JOFR1; } set { _JOFR1 = value; } }

        /// <summary>
        /// ADC injected channel data offset register 2, Address offset: 0x18
        /// </summary>
        public UInt32 JOFR2 { get { return _JOFR2; } set { _JOFR2 = value; } }

        /// <summary>
        /// ADC injected channel data offset register 3, Address offset: 0x1C
        /// </summary>
        public UInt32 JOFR3 { get { return _JOFR3; } set { _JOFR3 = value; } }

        /// <summary>
        /// ADC injected channel data offset register 4, Address offset: 0x20 
        /// </summary>
        public UInt32 JOFR4 { get { return _JOFR4; } set { _JOFR4 = value; } }

        /// <summary>
        /// ADC watchdog higher threshold register, Address offset: 0x24
        /// </summary>
        public UInt32 HTR { get { return _HTR; } set { _HTR = value; } }

        /// <summary>
        /// ADC watchdog lower threshold register, Address offset: 0x28
        /// </summary>
        public UInt32 LTR { get { return _LTR; } set { _LTR = value; } }

        /// <summary>
        /// ADC regular sequence register 1, Address offset: 0x2C
        /// </summary>
        public UInt32 SQR1 { get { return _SQR1; } set { _SQR1 = value; } }

        /// <summary>
        /// ADC regular sequence register 2, Address offset: 0x30
        /// </summary>
        public UInt32 SQR2 { get { return _SQR2; } set { _SQR2 = value; } }

        /// <summary>
        /// ADC regular sequence register 3, Address offset: 0x34 
        /// </summary>
        public UInt32 SQR3 { get { return _SQR3; } set { _SQR3 = value; } }

        /// <summary>
        /// ADC injected sequence register, Address offset: 0x38
        /// </summary>
        public UInt32 JSQR { get { return _JSQR; } set { _JSQR = value; } }

        /// <summary>
        /// ADC injected data register 1, Address offset: 0x3C
        /// </summary>
        public UInt32 JDR1 { get { return _JDR1; } set { _JDR1 = value; } }

        /// <summary>
        /// ADC injected data register 2, Address offset: 0x40
        /// </summary>
        public UInt32 JDR2 { get { return _JDR2; } set { _JDR2 = value; } }

        /// <summary>
        /// ADC injected data register 3, Address offset: 0x44
        /// </summary>
        public UInt32 JDR3 { get { return _JDR3; } set { _JDR3 = value; } }

        /// <summary>
        /// ADC injected data register 4, Address offset: 0x48
        /// </summary>
        public UInt32 JDR4 { get { return _JDR4; } set { _JDR4 = value; } }

        /// <summary>
        /// ADC regular data register, Address offset: 0x4C
        /// </summary>
        public UInt32 DR { get { return _DR; } set { _DR = value; } }

        #endregion

        #region Registers...

        /// <summary>
        /// ADC Common status register, Address offset: ADC1 base address + 0x300 
        /// </summary>
        public Register CSR_Register;

        /// <summary>
        /// ADC common control register, Address offset: ADC1 base address + 0x304
        /// </summary>
        public Register CCR_Register;  
   
        /// <summary>
        /// ADC common regular data register for dual AND triple modes, Address offset: ADC1 base address + 0x308
        /// </summary>
        public Register CDR_Register;     

        /// <summary>
        /// ADC status register, Address offset: 0x00
        /// </summary>
        public Register SR_Register;  
   
        /// <summary>
        /// ADC control register 1, Address offset: 0x04
        /// </summary>
        public Register CR1_Register;   
       
        /// <summary>
        /// ADC control register 2, Address offset: 0x08
        /// </summary>
        public Register CR2_Register;   
  
        /// <summary>
        /// ADC sample time register 1, Address offset: 0x0C
        /// </summary>
        public Register SMPR1_Register; 
  
        /// <summary>
        /// ADC sample time register 2, Address offset: 0x10 
        /// </summary>
        public Register SMPR2_Register;  

        /// <summary>
        /// ADC injected channel data offset register 1, Address offset: 0x14
        /// </summary>
        public Register JOFR1_Register;  
 
        /// <summary>
        /// ADC injected channel data offset register 2, Address offset: 0x18
        /// </summary>
        public Register JOFR2_Register;   

        /// <summary>
        /// ADC injected channel data offset register 3, Address offset: 0x1C
        /// </summary>
        public Register JOFR3_Register;   

        /// <summary>
        /// ADC injected channel data offset register 4, Address offset: 0x20 
        /// </summary>
        public Register JOFR4_Register;  

        /// <summary>
        /// ADC watchdog higher threshold register, Address offset: 0x24
        /// </summary>
        public Register HTR_Register;  
   
        /// <summary>
        /// ADC watchdog lower threshold register, Address offset: 0x28
        /// </summary>
        public Register LTR_Register; 
    
        /// <summary>
        /// ADC regular sequence register 1, Address offset: 0x2C
        /// </summary>
        public Register SQR1_Register; 
   
        /// <summary>
        /// ADC regular sequence register 2, Address offset: 0x30
        /// </summary>
        public Register SQR2_Register;  
  
        /// <summary>
        /// ADC regular sequence register 3, Address offset: 0x34 
        /// </summary>
        public Register SQR3_Register;  
 
        /// <summary>
        /// ADC injected sequence register, Address offset: 0x38
        /// </summary>
        public Register JSQR_Register;  
 
        /// <summary>
        /// ADC injected data register 1, Address offset: 0x3C
        /// </summary>
        public Register JDR1_Register;   

        /// <summary>
        /// ADC injected data register 2, Address offset: 0x40
        /// </summary>
        public Register JDR2_Register;   
 
        /// <summary>
        /// ADC injected data register 3, Address offset: 0x44
        /// </summary>
        public Register JDR3_Register;  
  
        /// <summary>
        /// ADC injected data register 4, Address offset: 0x48
        /// </summary>
        public Register JDR4_Register;  
  
        /// <summary>
        /// ADC regular data register, Address offset: 0x4C
        /// </summary>
        public Register DR_Register;      

        #endregion

        public AnalogToDigitalConverter(UInt32 ADCx_BASE)
        {
            CSR_Register = new Register(STM32F4xx.ADC1_BASE + CSR);
            CCR_Register = new Register(STM32F4xx.ADC1_BASE + CCR);
            CDR_Register = new Register(STM32F4xx.ADC1_BASE + CDR); 
    
            SR_Register = new Register(ADCx_BASE + SR);  
            CR1_Register = new Register(ADCx_BASE + CR1);   
            CR2_Register = new Register(ADCx_BASE + CR2);   
            SMPR1_Register = new Register(ADCx_BASE + SMPR1);
            SMPR2_Register = new Register(ADCx_BASE + SMPR2);  
            JOFR1_Register = new Register(ADCx_BASE + JOFR1);  
            JOFR2_Register = new Register(ADCx_BASE + JOFR2);   
            JOFR3_Register = new Register(ADCx_BASE + JOFR3);   
            JOFR4_Register = new Register(ADCx_BASE + JOFR4);  
            HTR_Register = new Register(ADCx_BASE + HTR);  
            LTR_Register = new Register(ADCx_BASE + LTR); 
            SQR1_Register = new Register(ADCx_BASE + SQR1); 
            SQR2_Register = new Register(ADCx_BASE + SQR2);  
            SQR3_Register = new Register(ADCx_BASE + SQR3);  
            JSQR_Register = new Register(ADCx_BASE + JSQR);  
            JDR1_Register = new Register(ADCx_BASE + JDR1);   
            JDR2_Register = new Register(ADCx_BASE + JDR2);   
            JDR3_Register = new Register(ADCx_BASE + JDR3);  
            JDR4_Register = new Register(ADCx_BASE + JDR4);  
            DR_Register = new Register(ADCx_BASE + DR);
        }

    } // END of Class...

    public sealed class DigitalToAnalogConverter
    {
        #region Private's...

        private uint _CR = 0x00;
        private uint _SWTRIGR = 0x04;
        private uint _DHR12R1 = 0x08;
        private uint _DHR12L1 = 0x0C;
        private uint _DHR8R1 = 0x10;
        private uint _DHR12R2 = 0x14;
        private uint _DHR12L2 = 0x18;
        private uint _DHR8R2 = 0x1C;
        private uint _DHR12RD = 0x20;
        private uint _DHR12LD = 0x24;
        private uint _DHR8RD = 0x28;
        private uint _DOR1 = 0x2C;
        private uint _DOR2 = 0x30;
        private uint _SR = 0x34;

        #endregion

        #region Properties...

        /// <summary>
        /// DAC control register, Address offset: 0x00
        /// </summary>
        public UInt32 CR { get { return _CR; } set { _CR = value; } }

        /// <summary>
        /// DAC software trigger register, Address offset: 0x04
        /// </summary>
        public UInt32 SWTRIGR { get { return _SWTRIGR; } set { _SWTRIGR = value; } }

        /// <summary>
        /// DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08
        /// </summary>
        public UInt32 DHR12R1 { get { return _DHR12R1; } set { _DHR12R1 = value; } }

        /// <summary>
        /// DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C
        /// </summary>
        public UInt32 DHR12L1 { get { return _DHR12L1; } set { _DHR12L1 = value; } }

        /// <summary>
        /// DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10
        /// </summary>
        public UInt32 DHR8R1 { get { return _DHR8R1; } set { _DHR8R1 = value; } }

        /// <summary>
        /// DAC channel2 12-bit right aligned data holding register, Address offset: 0x14
        /// </summary>
        public UInt32 DHR12R2 { get { return _DHR12R2; } set { _DHR12R2 = value; } }

        /// <summary>
        /// DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18
        /// </summary>
        public UInt32 DHR12L2 { get { return _DHR12L2; } set { _DHR12L2 = value; } }

        /// <summary>
        /// DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C
        /// </summary>
        public UInt32 DHR8R2 { get { return _DHR8R2; } set { _DHR8R2 = value; } }

        /// <summary>
        /// Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20
        /// </summary>
        public UInt32 DHR12RD { get { return _DHR12RD; } set { _DHR12RD = value; } }

        /// <summary>
        /// DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24
        /// </summary>
        public UInt32 DHR12LD { get { return _DHR12LD; } set { _DHR12LD = value; } }

        /// <summary>
        /// DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28
        /// </summary>
        public UInt32 DHR8RD { get { return _DHR8RD; } set { _DHR8RD = value; } }

        /// <summary>
        /// DAC channel1 data output register, Address offset: 0x2C
        /// </summary>
        public UInt32 DOR1 { get { return _DOR1; } set { _DOR1 = value; } }

        /// <summary>
        /// DAC channel2 data output register, Address offset: 0x30
        /// </summary>
        public UInt32 DOR2 { get { return _DOR2; } set { _DOR2 = value; } }

        /// <summary>
        /// DAC status register, Address offset: 0x34
        /// </summary>
        public UInt32 SR { get { return _SR; } set { _SR = value; } }

        #endregion

        #region Registers...

        /// <summary>
        /// DAC control register, Address offset: 0x00
        /// </summary>
        public Register CR_Register; 
      
        /// <summary>
        /// DAC software trigger register, Address offset: 0x04
        /// </summary>
        public Register SWTRIGR_Register; 
  
        /// <summary>
        /// DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08
        /// </summary>
        public Register DHR12R1_Register; 
  
        /// <summary>
        /// DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C
        /// </summary>
        public Register DHR12L1_Register; 
  
        /// <summary>
        /// DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10
        /// </summary>
        public Register DHR8R1_Register;
    
        /// <summary>
        /// DAC channel2 12-bit right aligned data holding register, Address offset: 0x14
        /// </summary>
        public Register DHR12R2_Register; 
  
        /// <summary>
        /// DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18
        /// </summary>
        public Register DHR12L2_Register;   

        /// <summary>
        /// DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C
        /// </summary>
        public Register DHR8R2_Register;
    
        /// <summary>
        /// Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20
        /// </summary>
        public Register DHR12RD_Register;  
 
        /// <summary>
        /// DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24
        /// </summary>
        public Register DHR12LD_Register;  
 
        /// <summary>
        /// DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28
        /// </summary>
        public Register DHR8RD_Register; 
   
        /// <summary>
        /// DAC channel1 data output register, Address offset: 0x2C
        /// </summary>
        public Register DOR1_Register;   
   
        /// <summary>
        /// DAC channel2 data output register, Address offset: 0x30
        /// </summary>
        public Register DOR2_Register;  
    
        /// <summary>
        /// DAC status register, Address offset: 0x34
        /// </summary>
        public Register SR_Register;       

        #endregion

        public static DigitalToAnalogConverter DAC = new DigitalToAnalogConverter(STM32F4xx.DAC_BASE);

        public DigitalToAnalogConverter(UInt32 DAC_BASE)
        {
            CR_Register = new Register(DAC_BASE + CR);
            SWTRIGR_Register = new Register(DAC_BASE + SWTRIGR);
            DHR12R1_Register = new Register(DAC_BASE + DHR12R1);
            DHR12L1_Register = new Register(DAC_BASE + DHR12L1);
            DHR8R1_Register = new Register(DAC_BASE + DHR8R1);
            DHR12R2_Register = new Register(DAC_BASE + DHR12R2);
            DHR12L2_Register = new Register(DAC_BASE + DHR12L2);
            DHR8R2_Register = new Register(DAC_BASE + DHR8R2);
            DHR12RD_Register = new Register(DAC_BASE + DHR12RD);
            DHR12LD_Register = new Register(DAC_BASE + DHR12LD);
            DHR8RD_Register = new Register(DAC_BASE + DHR8RD);
            DOR1_Register = new Register(DAC_BASE + DOR1);
            DOR2_Register = new Register(DAC_BASE + DOR2);
            SR_Register = new Register(DAC_BASE + SR); 
        }

    } // END of Class...
